1. Field of the Invention
The present invention relates to a method for fabricating interconnections of pure Cu or a Cu alloy (hereinafter generically referred to as “Cu-based metal”) in semiconductor devices. Specifically, it relates to a method for fabricating Cu-based interconnections in semiconductor devices, such as Si semiconductor devices, typified by ultra-large scale integrated circuits (ULSL) by fabricating a thin film of a Cu-based metal on a groove, such as a via hole or a trench, arranged in a dielectric film by sputtering (physical vapor deposition), and embedding the Cu-based metal into the groove by reflowing at high temperature and high pressure to thereby fabricate the Cu-based interconnection.
2. Description of the Related Art
The design rule of semiconductor devices such as large-scale integrated circuits (LSIs) has more and more reduced shrank for larger packing densities and higher-speed signal transmission. The interconnection pitch, width and interval between interconnections, for example, have more and more reduced. These techniques mainly aim at faster devices. Such a device, however, has an increased interconnection resistance with a decreasing size and an increasing packing density of its interconnection circuit, and the increased interconnection resistance causes delay of signal transmission. To avoid this, interconnection materials having a lower electric resistance have been proposed. Namely, Cu-based materials have been used as interconnections, since such Cu-based materials have a lower electric resistance than conventional Al-based interconnection materials.
For larger packing densities and higher capabilities, the Cu-based interconnection is designed to have a multilayer structure, for example, by a damascene interconnection process (e.g., Japanese Patent Application Laid-Open (JP-A) No. 10-79428). In the damascene process, for example, an interlayer dielectric film typically of silicon oxide or silicon nitride is deposited on a semiconductor substrate, interconnection grooves such as trenches and via holes for embedded interconnection, and interlayer contact holes are deposited in the interlayer dielectric film, a TaN thin film is deposited inside the interconnection grooves, a seed layer of a Cu thin film is then deposited, the Cu thin film is embedded into the interconnection grooves and the interlayer contact holes by electrochemical deposition (electroplating), unnecessary interconnection material deposited on the other region than the interconnection grooves and the interlayer contact holes is removed by chemical mechanical polishing (CMP) to remain the interconnection material only in the interconnection grooves and the interlayer contact holes to thereby yield interconnections. In addition, a dual damascene interconnection process has been employed. In the dual damascene process, interlayer contact holes are fabricated during the formation of interconnection grooves, and the resulting interconnection grooves and interlayer contact holes are simultaneously filled with an interconnection material (metal) to thereby yield interconnections.
LSI interconnections have been down-sized more and more in accordance with the “road map”. The resulting interconnection grooves and interlayer contact holes have decreasing widths and diameters, respectively, and have increasing aspect ratios (the ratio of the depth to the diameter) The process for fabricating Cu interconnections by electrochemical deposition, however, cannot satisfactorily embed the Cu interconnection material into grooves having minute dimensions. Thus, Cu cannot significantly perfectly embedded into via holes having high aspect ratios, and via holes and trenches having small diameters with interconnection width of 100 nm or less. Particularly, on the interconnection design rule of 0.1 μm or less, the via holes and trenches have further decreasing dimensions and further increasing aspect ratios, and the Cu-based material cannot significantly be embedded thereinto completely, which fails to provide reliable interconnections.
In addition to the above requirement (full embedment), such Cu-based interconnections must have a low electric resistivity ρ equal to or less than about 3 to 4 μΩcm, sufficient reliability in contact (formation of reliable contacts) and sufficient reliability in interconnection. More specifically, the Cu-based interconnections must have resistance against breaks caused by stress migration (SM resistance) and resistance against breaks caused by electromigration (EM resistance). The conventional damascene interconnection process using electrochemical deposition cannot significantly provide Cu-based interconnections having properties equivalent to those of bulk Cu materials and fails to provide Cu-based interconnections satisfying all the above requirements.
Deposition of Cu interconnections by chemical vapor deposition (CVD) has been proposed as a possible candidate for perfectly embedding a Cu-based metal into interconnection grooves and interlayer contact holes. The deposition by CVD, however, cannot significantly yield high-purity interconections and brings about high cost. To avoid these problems, the present inventors have focused attention to improvement in the dual damascene interconnection process. The dual damascene process has increasingly employed mainly in customized ICs in Japan and will be further employed for fabricating Cu interconnections.
To improve the interconnection reliability, the use of Cu alloys instead of pure Cu as a material for Cu interconnections has been proposed. Such Cu alloys have a higher yield stress and provide higher adhesion between the interconnection and a barrier film such as a TaN thin film. Such proposed Cu alloy materials for the Cu interconnections are roughly classified as five groups, i.e., Cu—Ti alloys, Cu—Zr alloys, Cu—Sn alloys, Cu—Al alloys and Cu—Mg alloys. However, there is a limit in the type of Cu alloy materials for fabricating Cu-based interconnections in the dual damascene interconnection process using electrochemical deposition.
The disadvantages in the dual damascene interconnection process using electrochemical deposition may be effectively solved by sputtering a Cu alloy interconnection material, and subjecting the work to high temperature and high pressure reflowing. In the high temperature and high-pressure reflowing, a thin film 5 made of a Cu-based metal is deposited on a dielectric film 2 by sputtering, which dielectric film 2 has grooves such as a via hole (interconnection contact hole) 3 and a trench (interconnection groove) 6, so that the thin film 5 bridges the grooves (FIG. 1A); and a pressure (load) is isotropically applied vertically to the surface of the thin film to thereby press the Cu-based metal into the grooves (FIG. 1B). In this procedure, for example, hydrostatic pressure is applied at a pressure higher than normal pressure as described in JP-A No. 05-211238.
JP-A No. 2001-7050, for example, proposes a technique of depositing a metal material including copper, a copper alloy, silver, or a silver alloy so as to cover a dielectric film having holes and trenches over a substrate, and the holes and trenches are filled with the metal material as a result of anneal process, to thereby fabricate an interconnection film.
This technique, however, still has the following disadvantages. Specifically, the deposited Cu alloy thin film are not satisfactorily pressed into the holes and trenches by high temperature and high pressure reflowing unless the thin film is continuous and air-tight. In addition, the thin film of Cu-based metal cannot further be pressed into the holes and trenches if it deforms and breaks. Among such Cu-based thin films, those deposited by sputtering have lower reflowability (flowability at high temperatures) than Cu-based thin films deposited by electrochemical deposition. Thus, improvement in reflowability of such Cu-based thin films deposited by sputtering is an important issue in the damascene interconnection process.
In addition, considerably high temperature and high pressure are required for embedding such a Cu-based material into via holes and trenches having minute dimensions and having a high aspect ratio. Such high temperature and high pressure, however, cannot be significantly achieved actually. A demand has therefore been made to provide a technique for embedding such a Cu-based material into holes and trenches under relatively mild conditions.